Huawei Ascend 950 at About 8,000 TPP; China's AI Stack Stalls at HBM, SMIC

On Huawei's published rates for 8-bit (FP8) and 4-bit (FP4) math, and if those rates are dense, its Ascend 950 accelerator works out to about 8,000 on the total processing performance (TPP) scale of the January 2026 US export rule, well under its 21,000 line. Layer by layer, China's AI chip stack no longer stalls at chip design; it stalls at memory and at wafers.

That 8,000 is Voltgrid's arithmetic. Huawei does not label its rates dense (every value computed) or sparse (zeros skipped, which reads higher) and has published no FP16, BF16 or INT8 rate for the 950; the rule scores a chip's best format, so 8,000 is the score of the formats Huawei published, and about 4,000 if the rates are sparse. Even so, China can now design chips inside the band the United States reviews case by case for export to it. The Ascend 960DT, due in Q1 2027, would be the first Ascend part over one of the rule's lines, on a 9,600 GB/s memory bandwidth that only Tom's Hardware has reported. Supply holds it back: Chinese memory maker CXMT's first HBM3E, the high-bandwidth memory AI chips need, is reported at 20% to 30% yields, and Huawei rotating chairman Eric Xu said in September 2026, per Reuters, that Huawei lacks the capacity to meet demand even in China.

BIS Rule in Two Numbers

The Bureau of Industry and Security (BIS) rule, effective Jan. 15, 2026, moved license review for exports to China and Macau from a presumption of denial to case-by-case, but only for chips under 21,000 TPP and under 6,500 GB/s of total DRAM bandwidth. It names NVIDIA's H200 and AMD's MI325X as examples. China-bound TPP may not exceed 50% of what the exporter shipped to US customers of the same product, and a qualified US lab checks every shipment. The Federal Register shows no newer BIS rule on advanced computing for China.

Technical Note 2 to export category 3A090 defines TPP as twice the peak multiply-accumulate rate times the bit length of the operation, which equals datasheet TFLOPS (trillions of floating-point operations per second; 1,000 make a PFLOPS, 1 million an EFLOPS) times bits. It counts dense math and takes the chip's highest-scoring format. NVIDIA lists the H200 at 3,958 TFLOPS of FP8 with sparsity, or 1,979 dense, which scores 15,832 (1,979 × 8). Memory is scored separately, so a chip can pass on compute and fail on bandwidth. FP4 adds nothing when its rate is exactly twice FP8, as on the 950 and 960DT; where it is more than double, the higher FP4 result counts.

Rates below are in TFLOPS. The older Ascend 910C: 752 TFLOPS dense BF16 × 16 = 12,032 TPP at 3.2 TB/s, per a Huawei paper; it outscores the 950 on published figures, but not like for like: Huawei gave a 16-bit rate for it and none for the 950. Ascend 950PR and 950DT, the same 950 die with different memory: 1,000 TFLOPS FP8 × 8 = 8,000, the 950DT at 4.0 TB/s. NVIDIA H200: 15,832 at 4.8 TB/s. Ascend 960DT: 2,000 FP8 × 8 = 16,000, but a reported 9.6 TB/s, over the 6.5 TB/s line. Ascend 960PR: its reported 8,000 TFLOPS of FP4 × 4 = 32,000, over the compute line if dense, at a reported 2.4 TB/s. Ascend 970: a reported 3,600 FP8 × 8 = 28,800, but its reported 14,000 FP4 × 4 = 56,000 is higher; Huawei's 2025 keynote, which said 970 specs were not final, printed 4 PFLOPS of FP8, or 4,000 × 8 = 32,000. The rule governs US exports, not Huawei's chips; it is only a yardstick here.

Huawei Ascend Chips: Confirmed Versus Reported

Huawei's September 2025 keynote text lists the Ascend 950 die at 1 PFLOPS in FP8 and 2 PFLOPS in MXFP4, and the 950DT with 144 GB of Huawei's HiZQ 2.0 memory at 4 TB/s. Its 2026 keynote confirms dates only: Ascend 960DT in Q1 2027, three quarters early; 960PR in Q3 2027; 970 in 2028; 980 in 2029. The 960 and 970 memory figures, the revised 960PR and 970 compute figures and the 950PR's 128 GB at 1.6 TB/s are reported by Tom's Hardware from Huawei's slides; Huawei's text does not print them.

On FP8, if Huawei's rate is dense, the 950 offers about half the H200's dense rate (1,000 ÷ 1,979 = 0.51). The 950DT matches the H200 on memory capacity, 144 GB against 141 GB, at 83% of its bandwidth (4.0 ÷ 4.8 TB/s).

Two figures conflict. Huawei's 2025 keynote rated the 950 die at 2 PFLOPS of FP4, but Zhang Dixuan, head of Huawei's Ascend computing business, gave the Atlas 350 card built on the 950PR 1.56 PFLOPS of FP4 at its March 2026 launch, per the South China Morning Post via TrendForce. Mydrivers reported the card at 112 GB and 1.4 TB/s, against Tom's Hardware's 128 GB at 1.6 TB/s. Huawei has not reconciled them.

Cambricon, a Chinese AI chip designer, reported third-quarter revenue of CNY 3.531 billion, up 104.47% from a year earlier, and net profit of CNY 1.404 billion, company figures carried by Yicai Global. Analysts had expected about CNY 6.26 billion, and Bloomberg's report, as relayed by The Next Web, tied the miss to chip supply; Cambricon credited market expansion and cited no supply limit, as Voltgrid reported. It kept its 2026 revenue target of at least CNY 13.5 billion, so after CNY 9.526 billion in nine months the fourth quarter must bring at least CNY 3.974 billion, 12.5% above the third.

Where It Stalls: SMIC N+3 Wafers, CXMT HBM3E

Manufacturing is the first limit. TechInsights' teardown of Huawei's Kirin 9030 confirmed the N+3 process of Chinese foundry SMIC: a denser version of its 7nm-class technology made without extreme ultraviolet (EUV) lithography, still significantly less dense than TSMC's and Samsung's 5nm. The Ascend 950's node is reported, not confirmed: Tom's Hardware says SMIC makes the 950PR on N+3, and TrendForce cites Eastmoney for the 950DT. TrendForce estimated in December 2025 that N+3 and N+4 yield around 20% and called N+2 China's most stable high-yield advanced node; SMIC has published no yield figure.

Memory is the second. CXMT plans limited HBM3E production at yields of about 20% to 30%, against about 70% at SK hynix, two people told Reuters on Oct. 28: a gap of 40 to 50 percentage points. One said it tested closer to SK hynix's older HBM3 and will cost more than imported parts; CXMT did not comment, as Voltgrid reported. The start date conflicts: The Information reported at the end of August 2026 that CXMT had begun small-scale HBM3E output, as carried by Korea JoongAng Daily, while one Reuters source put limited production within two months of late October. CXMT has confirmed neither.

SK hynix said HBM4, the generation after HBM3E, began shipping in earnest in the third quarter and becomes its mainstream product from the fourth. Huawei pairs its 950 chips with HBM it brands as its own, HiBL 1.0 and HiZQ 2.0; its keynote names no maker, and Tom's Hardware reported they were developed with CXMT, which neither company has confirmed. The Information reported smuggled HBM3E reaching Huawei's customers at about $4,000 a unit, which SK hynix denies supplying, as Voltgrid reported.

Atlas SuperPoD Systems and DeepSeek Demand

Huawei answers weaker chips with bigger systems. The Atlas 950 SuperPoD links up to 8,192 Ascend 950DT chips for 8 EFLOPS of FP8 in 160 cabinets, 128 of them for compute, over about 1,000 square meters. Huawei's 2025 roadmap dated it Q4 2026; its September 2026 keynote says it is in large-scale commercial use, without naming customers or counts. Footprint is the cost: on peak FP8, if Huawei's figure is dense, a full Atlas 950 SuperPoD equals about 6.5 of NVIDIA's Vera Rubin NVL72 racks at 1,260 PFLOPS each (8,192 × 1 PFLOPS ÷ 1,260), spread over 128 compute cabinets.

Demand is not the problem. TrendForce reported in June 2026 that DeepSeek V4 was running on the Ascend 950 platform, and DeepSeek added Ascend support to six code repositories, SemiAnalysis said. Caiwen News reports DeepSeek plans to train V5 mainly on Ascend 950 chips in 2027, as Voltgrid reported; neither company has confirmed it.

This reading could be wrong in either direction. No independent lab has published a benchmark or teardown of any Ascend 950-series chip, so every per-chip figure here is Huawei's claim or a report. Real systems are smaller than the maximums: Huawei showed an Atlas 950 SuperPoD with 1,024 accelerator cards in July 2026, Tom's Hardware noted, and Huawei Cloud's Ascend 950 service is a 1,024-card cluster rated at 1 EFLOPS of FP8, TechNode reported. The stall may also be shorter than it looks: Huawei pulled the 960DT forward three quarters, says it has its own HBM, and says 61% of developers on CANN, its Ascend software stack, are now outsiders.

What it means for engineers and investors: in 2026 a Chinese buyer can get H200-class memory capacity from Huawei but about half the H200's FP8 rate per chip if Huawei's figure is dense (a quarter if sparse), so on peak FP8 a cluster needs at least twice the chips, cabinets and links. The scarce inputs are HBM stacks and N+2 or N+3 wafers, not designs. CXMT's yields, SMIC's capacity and Huawei-branded HBM will set China's AI output in 2027.

What to Watch

Nov. 12, after the Hong Kong and Shanghai close (about 3 a.m. Eastern): SMIC releases third-quarter results, the company said, with a call at 08:30 China time on Nov. 13 (7:30 p.m. Eastern on Nov. 12); a Tiger Brokers preview put consensus revenue at $3.09 billion. Nov. 30: Huawei Cloud takes its Ascend 950 cluster service to global markets, its CEO said, per TechNode, though Xu said Huawei ships only limited volumes abroad. By the end of December: CXMT's limited HBM3E production on one Reuters source's timeline. Q4 2026: a first named customer or shipment count for the full Atlas 950 SuperPoD, and HBM4 as SK hynix's mainstream product. Q1 2027: the Ascend 960DT, the first Ascend part over a BIS line if its reported 9,600 GB/s holds. Q3 2027: the Ascend 960PR. 2028: the Ascend 970, over 21,000 TPP on every version of its figures if they are dense.