UMC, AP Memory Tape Out Gen2D Silicon Capacitors for AI Power Delivery
UMC and AP Memory said S-SiCap Gen2D deep-trench silicon capacitors passed initial functional validation in Q3 2026. System-level tests in substrate packages come next, and no customer is named.
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UMC and AP Memory say S-SiCap Gen2D capacitors completed initial functional validation in Q3 2026, according to their joint release.
Illustration (AI-generated)
UMC and AP Memory said on Oct. 22 that AP Memory's S-SiCap Gen2D discrete silicon capacitors, built on UMC's deep trench capacitor (DTC) technology, completed tape-out and initial functional validation in the third quarter of 2026. The two companies announced the work in a joint release from Hsinchu.

UMC and AP Memory say deep trench capacitors can sit in the interposer, substrate or landside; system-level tests in substrate packages come next.
Illustration (AI-generated)
The partnership pairs UMC's DTC process and wafer manufacturing with AP Memory's silicon capacitor designs and system-level integration. According to the release, a deep trench capacitor can sit in the interposer, the substrate or on the landside of an advanced package, depending on how a system is designed. The work targets power delivery for AI and high-performance computing (HPC) systems.



