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SK hynix has approached suppliers about producing iHBM, a base-die cooling design it says cuts HBM thermal resistance by more than 30%, ETNews reports; HBM5 use is expected around 2029.
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SK hynix's own iHBM graphic from its newsroom: the ICE block sits beside the HBM stack at the base-die D2D PHY. It is a vendor illustration, not a photo of a product.
Image: SK hynix
Source · Press image from the SK hynix newsroom, used for news reporting.
SK hynix has begun talks with materials, parts and equipment suppliers in South Korea and abroad about producing iHBM, its heat-management design for high-bandwidth memory (HBM), the Korean business daily ETNews reported on Oct. 21.
According to ETNews, the discussions covered how iHBM would be applied in real products and what a mass-production plan would look like. The paper cited an unnamed official at a SK hynix partner company, who said the chipmaker is sounding out supplier cooperation to commercialize the design and appears to be checking whether volume production is feasible. SK hynix has not announced a production schedule, and Voltgrid found no company statement on the talks.
Why it matters for AI power and cooling: heat is one of the hardest limits on HBM, ETNews notes. The base die, which carries the die-to-die physical layer (D2D PHY) linking the memory to the GPU, gets hotter as compute load and stack height rise. Its heat has to pass up through the DRAM core dies above it. Weak thermal control cuts power efficiency and can cause slowdowns, system errors and shorter lifetimes. A memory stack that sheds heat through an extra path could ease the cooling load that accelerator makers and data-center operators must handle at rack level.
SK hynix says iHBM cuts thermal resistance by more than 30%, a vendor claim reported by ETNews.
Illustration (AI-generated)
SK hynix introduced iHBM in May. The design places integrated cooling elements (ICE) at the D2D PHY on the base die, which creates a second route for heat to leave the stack. SK hynix has said the approach lowers thermal resistance by more than 30%. That figure is the company's own claim, and it describes thermal resistance, not a gain in power efficiency or a measured result in a customer system.
According to ETNews, iHBM uses the wafer-level packaging process built on Advanced MR-MUF, the molded-underfill method SK hynix already uses to fill the gaps between stacked HBM chips in a single step. For that reason the paper expects a supplier chain similar to today's HBM. SK hynix is also reported to be considering widening its supplier base beyond that existing chain to improve iHBM performance and productivity.
ETNews says SK hynix aims to apply iHBM starting with HBM5, which its roadmap would place around 2029. The paper adds that the company is now validating HBM5 using TSMC's CoWoS advanced packaging.
Rivals are working on the same D2D PHY heat problem. As TrendForce reported in June, Samsung Electronics showed a Heat Path Block (HPB) at Computex that adds a separate thermal path in that region, and the chief technology officer of Samsung's chip (DS) division said it was already implemented in HBM4E. Micron is taking a different route with low-power designs and through-silicon-via trench cooling, the same report said, citing Korean press. TrendForce also cited a Korean report that next-generation GPU power is heading toward 1,000 W per chip. Voltgrid News reported earlier on Samsung's restart of Fab 5 at Pyeongtaek.
The supplier talks rest on unnamed industry sources, and ETNews did not name any supplier. No customer has been named for iHBM, and SK hynix has not given a ramp date, a capacity figure or a price. The 2029 HBM5 timing is the paper's reading of the roadmap, not a company commitment. Whether the 30% thermal-resistance gain holds in volume parts, and what it means for GPU power limits, will only be clear once samples reach customers.
