Snapdragon X2 Elite 'Performance' Cores Look Like Efficiency Cores, Lab Says

Qualcomm's six "Performance" Oryon cores in the Snapdragon X2 Elite Extreme are 4-wide, 3.6 GHz designs that appear aimed at saving power rather than adding throughput, Chips and Cheese concluded from microbenchmarks published on Oct 24. The lab notes that Qualcomm's slides do not state that aim.

The independent lab ran its tests on an X2E-96-100 inside an Asus Zenbook A16 (UX3607OA) that Asus sampled. It measured a 128 KB L1 instruction cache and a 64 KB L1 data cache that returns data in 3 cycles, or 4 with indexed addressing. Behind them sits one L2 cache shared by all six cores at 21 cycles, with no private mid-level cache per core, a layout the lab likens to Apple's M1. Together the six cores pulled just over 400 GB/s of read bandwidth from that L2, about 18 bytes per core cycle. Chips and Cheese's verdict is that "efficiency" describes the cluster better than Qualcomm's own label.

The finding matters for how Qualcomm sells the X2 Elite. Its product brief leans on multi-day battery life and on spreading work across the CPU, GPU and NPU to cut power. A narrow, lower-clocked cluster that holds background tasks and light apps without waking the 9-wide, 5 GHz Prime cores is the mechanism behind that pitch. The lab notes that the hybrid layout breaks with the all-big-core approach of Qualcomm's earlier in-house core designs. The measurements show the design intent, not the watts, so the battery-life case remains a vendor claim until a lab puts this cluster on a power meter.

Inside the Snapdragon X2 Elite Efficiency Cluster

Core width is the number of instructions a core can push through per cycle. Wider cores can do more per cycle, but they carry more dependency-checking logic that sits idle whenever the pipeline stalls. Chips and Cheese sets Qualcomm's 4-wide, 3.6 GHz core against Intel's 8-wide, 4.6 GHz Skymont efficiency core and Qualcomm's own 9-wide, 5 GHz Prime cores on the same chip. It argues that 4-wide is a sensible point for less critical work, because each extra slot of width brings smaller returns.

Inside, the lab counted four integer ALU ports, each fed by a 19-entry scheduler queue, and two floating-point and vector ports. The core supports SVE2 and SME, Arm's scalable vector and matrix extensions, but with a 128-bit vector length. SVE therefore adds new instructions here, not extra compute throughput. Branch-direction prediction across Geekbench 7 workloads came out roughly on par with Arm's Neoverse N2 and ahead of the Neoverse N1. The address-translation buffers handle 4 KB and 64 KB memory pages but not 16 KB ones.

Qualcomm's brief lists the X2E-96-100 with 18 cores: 12 Prime cores at 4.4 GHz across all cores and 5.0 GHz on one or two, plus the 6 Performance cores at 3.6 GHz, with 53 MB of total cache on a 3nm process. Qualcomm gives it LPDDR5x memory on a 192-bit bus at 228 GB/s and an 80 TOPS (INT8) NPU. The X2E-90-100 and X2E-88-100, the 18-core parts below the Extreme, clock their Performance cores at 3.4 GHz and list 152 GB/s on a 128-bit bus. Chips and Cheese did not report a total DRAM bandwidth figure, so the 228 GB/s is Qualcomm's number alone.

The chip work comes as Qualcomm prepares job cuts while it shifts toward AI data-center and edge chips. The PC line still has to win on battery life and Windows on Arm, and this cluster is where that efficiency case is built.

What No Lab Has Measured on Power Yet

This is one lab's work. Chips and Cheese published no power or performance-per-watt figures for the cluster, and no per-core SPEC or Geekbench scores. It also does not say whether the same core design appears in Qualcomm's phone chips. The figure to watch is a second independent lab measuring how much power the six Performance cores draw on X2 Elite laptops, and no source has set a date for that.