TSMC Reportedly Weighs a CoWoS Price Rise of up to 20%

TSMC is reportedly weighing a price increase of up to 20% for CoWoS advanced packaging, TrendForce wrote on Oct. 27, citing supply-chain sources quoted by Taiwan's Commercial Times.

TrendForce said Commercial Times reported that foundries and outsourced assembly and test firms are considering another CoWoS rise in a band of 10% to 20%, as orders spread from AI graphics processors to server CPUs and custom ASICs. The same account says some packaging lead times have already lengthened. TSMC has not confirmed a new CoWoS price in the report, and TrendForce does not quote a company spokesman.

Lead times, and a separate wafer claim

Commercial Times, as carried by TrendForce, said tool lead times have moved to six to eight months, from a prior three to six months, because buyers are reserving delivery slots instead of pressing for discounts. It also said TSMC, which in past years sought price cuts or extra features at the same price, ordered equipment this year at existing prices without asking for those concessions. That account is attributed to supply-chain sources, not to a TSMC filing.

A separate Liberty Times report, also cited by TrendForce, says TSMC has settled plans to lift wafer prices by 3% to 6% from January 2027, with the steepest moves on advanced nodes such as 2nm and 3nm. That is a different claim from the CoWoS packaging talk, and it is likewise reported rather than posted on TSMC's investor site.

Two capacity estimates that do not match

Analysts cited by Commercial Times put monthly CoWoS output above 130,000 wafers in 2026, with a 200,000-wafer target in 2027, TrendForce wrote. Goldman Sachs, in the same TrendForce piece, projects 1.275 million CoWoS wafers for 2026, about 106,000 a month, then 2.73 million in 2027. The monthly readings do not agree. Neither figure is treated here as TSMC's own capacity guide.

TrendForce also relayed an earnings-call remark from TSMC chairman and chief executive C.C. Wei: packaging at five times a reticle is in mass production with strong yields, while nine-times and fourteen-times versions are in development, alongside CoPoS for larger packages. Commercial Times, via TrendForce, points to 2028 for the fourteen-times package. Seoul Economic Daily, citing Nomura and quoted by TrendForce, said final test for NVIDIA Blackwell takes about four times as long as Hopper, and that Rubin could take about seven times as long. Those test multiples are an analyst estimate, not a TSMC measurement.

How CoWoS sits on the bill

CoWoS, short for chip-on-wafer-on-substrate, is the packaging step that sets a logic die beside high-bandwidth memory on a silicon interposer before the part goes onto a substrate. A higher price, if TSMC imposes one, would land on the AI accelerators and custom chips that already depend on that step. The report does not say when a new price would take effect, or which customers would pay it.

What is not confirmed yet

No TSMC newsroom post or exchange filing in the sources read on Oct. 27 announces a CoWoS price change. The 20% figure is a ceiling sources described to Commercial Times, not a posted tariff. Tool orders at existing prices, and the January 2027 wafer band, come from other press accounts inside the same TrendForce article. The hike stays unconfirmed until TSMC or a customer states it.