CXMT 4F² DRAM Platform Passes Sample Validation; Server DDR5 Due End-2026

China's CXMT says it has completed engineering-sample validation of a sixth-generation DRAM process platform built on a 4F² vertical-channel design, and expects to send DDR5 server samples to customers by the end of 2026, Seoul Economic Daily and Global Times report.

The company said the validation means the platform has met its core performance targets on real wafers and can move to mass production after customer qualification. CXMT disclosed the validation at its third-quarter results briefing on Oct. 30, according to SBS News and Chinese outlets The Paper and IT Home, and repeated it in a statement to Global Times on Oct. 31. CXMT also said it is the first company to complete such validation. Both the validation and the sample date are CXMT's own claims; no speeds, capacities, yields or outside test results have been published.

The claim lands on a live dispute. On Oct. 21, as Voltgrid reported, Micron's chief technology officer said 4F² has fundamental scaling problems at the leading edge and that its density advantage over 6F² is "a bit of a myth." Seoul Economic Daily says CXMT's latest statement answers that point directly: the layout of word lines and bit lines matters, not only the spacing of capacitors, which is where Micron placed the limit.

How a 4F² DRAM Cell Differs From 6F²

DRAM stores each bit in a cell, and cell area is quoted in multiples of F², the square of the smallest feature the chip’s lithography can print. Mainstream DRAM uses a 6F² cell, Global Times notes. A 4F² cell takes about 33% less area, Seoul Economic Daily reports, so more bits fit in the same silicon. CXMT says its version stands the transistor upright, using a vertical surrounding gate to limit leakage.

Area is only part of the cost. Micron says capacitor spacing caps the density gain, and CXMT answers that word-line and bit-line layout counts too. CXMT has published no speed, capacity or yield figure for its 4F² DDR5 samples, so server buyers cannot yet say how many more gigabytes a DIMM slot would hold.

Why server memory matters

For AI infrastructure the target product matters more than the cell geometry. A DDR5 RDIMM is the registered module that fills server memory slots, so a working 4F² part would be judged on capacity per slot, error rates over round-the-clock operation and power per module. A CXMT official told Seoul Economic Daily on Oct. 12 that a DDR5 RDIMM must run 24 hours a day without errors at high speed, so its technical bar is higher, and that making it the first 4F² product means taking on server memory's hardest requirements directly.

Where the rivals stand

CXMT chief executive Cao Kanyu said at a Shanghai conference on Oct. 9 and 10, Securities Daily reported on Oct. 12, that a 4F² DDR5 RDIMM would launch by year-end. Seoul Economic Daily noted that, on announced timelines alone, that would put CXMT about two years ahead of Samsung Electronics, which is targeting 2028 for sub-10-nanometre DRAM using the structure. Micron, as above, says it will stay with 6F² and move toward 3D DRAM.

SK hynix said on its Oct. 28 earnings call that it will keep stretching 6F² with EUV before moving to 4F² or 3D DRAM, and gave no dates. SBS adds that SK hynix is also developing technology for a later move to 4F².

What is not confirmed yet

South Korean industry officials quoted by Seoul Economic Daily on Oct. 12 said the new cell's scope in the first product may be limited, and cautioned that applying a new cell and reaching stable volume production are separate problems. No third party has tested a CXMT 4F² part. The year-end target covers customer samples, not shipments in volume, and CXMT itself said the new product is about medium- to long-term competitiveness rather than short-term profit.

The next checkpoints are whether samples reach customers before Dec. 31, and whether CXMT discloses capacity, speed and yield. Until then, Micron's and SK hynix's 6F² roadmaps remain the volume baseline for server DRAM.