NVIDIA Rubin HBM4 Slows to 19.2 TB/s as AMD MI455X Leads on Paper

NVIDIA's shipping Rubin GPU keeps its promised compute but runs its HBM4 high-bandwidth memory at 19.2 TB/s, not 22 TB/s, and NVLink at 3 TB/s, not 3.6, its own spec pages show. That leaves AMD's Instinct MI455X ahead on vendor paper in both per-GPU memory bandwidth (23.3 TB/s) and capacity (432 GB against 288 GB), and it makes memory, not FLOPS, the spec on which the 2026-27 accelerator contest is now argued.

The cut to the eight-GPU board was the subject of our earlier report, NVIDIA HGX Rubin NVL8 memory bandwidth cut 26% to 130 TB/s, which followed our Oct. 26 story that the Vera Rubin page lists 19.2 TB/s, not 22. This piece sets the full set of revisions against the rival that benefits from them.

What NVIDIA Changed in Rubin's Shipping Specs

ServeTheHome laid out the revised figures in a report published at 03:00 UTC on Nov. 1, as first production hardware reaches customers. NVIDIA posted the new numbers on its web pages and in its architecture datasheet in September, the outlet said, crediting IT Home with spotting them; the earlier values had been labelled preliminary and subject to change. For one Rubin GPU, memory bandwidth falls from 22 TB/s to 19.2 TB/s and NVLink scale-up bandwidth from 3.6 TB/s to 3.0 TB/s, a 17% cut. Bidirectional scale-out networking rises from 0.4 TB/s to 0.45 TB/s. Capacity stays at 288 GB, and the compute figures are unchanged at 50 PFLOPS of NVFP4 inference (a sparse figure, per NVIDIA's footnote) and 35 PFLOPS of NVFP4 training (dense).

NVIDIA's Vera Rubin NVL72 page now lists the 72-GPU rack at 20.7 TB of HBM4 and 1,400 TB/s, with 216 TB/s of NVLink and 32.4 TB/s of scale-out bandwidth. ServeTheHome gives the preliminary rack figures as 1,580 TB/s, 260 TB/s and 28.8 TB/s. The HGX page lists HGX Rubin NVL8 at 2 TB of HBM4 and 130 TB/s, against a preliminary 2.3 TB and 176 TB/s, with dense NVFP4 training trimmed to 270 PFLOPS and FP8/FP6 training to 130 PFLOPS, per NVIDIA's footnote.

Two details matter for how far the numbers can be trusted. First, NVIDIA's pages disagree with each other: on Nov. 1 the same HGX page that shows the 130 TB/s board still carried an individual Rubin GPU table at 288 GB, 22 TB/s and 3.6 TB/s, the preliminary figures. Second, NVIDIA has not said why it revised anything, ServeTheHome reports.

Why the Rubin HBM4 Bandwidth Cut Matters

Memory bandwidth is interface width times pin speed. JEDEC's HBM4 standard gives each stack a 2,048-bit interface and targets 8 Gbps per pin, according to ServeTheHome. The outlet works out that NVIDIA's eight stacks would have needed about 10.75 Gbps per pin for 22 TB/s and now run at about 9.375 Gbps. Those pin speeds are ServeTheHome's calculations, not NVIDIA statements.

The step matters because large-model inference is mostly decode, generating one token at a time. Each token re-reads the model weights and the cached context, so bandwidth, not peak FLOPS, usually sets the pace. A GPU that kept its 50 PFLOPS of sparse NVFP4 inference but lost bandwidth has kept the figure that limits it least on that work. That is an inference about workloads, not a measured result: no independent lab has yet published Rubin bandwidth or token rates.

The supply chain suggests where the gap opened, though it does not prove it. In February Samsung said its mass-produced HBM4 ran at 11.7 Gbps per pin, and up to 13 Gbps in some cases, and Micron's finance chief said its HBM4 delivered over 11 Gbps and that Micron had pre-sold all the HBM4 it can make this year, The Register reported. Rubin's calculated 9.375 Gbps per pin is below the 11.7 Gbps Samsung and the over-11 Gbps Micron cite for their own parts, but neither source says which suppliers' stacks or speed grades ship on Rubin. ServeTheHome lists memory-controller speed, stack speed or stack yield as the obvious explanations, and calls them assumptions.

AMD took the other route to the same bandwidth class. Its MI455X page lists 12 HBM4 stacks, 432 GB and 23.3 TB/s of peak memory bandwidth, and ServeTheHome reports AMD runs those stacks at 7.6 Gbps per pin. More stacks at a slower, easier speed gives AMD more capacity and more bandwidth on paper. If NVIDIA's revision is a supply limit, as ServeTheHome suspects, then the two designs read as two answers to the same constraint, and AMD's answer asked less of the memory makers.

The eight-GPU board took the deeper cut. ServeTheHome argues that 2 TB across eight GPUs leaves roughly 250-252 GB per GPU, which would mean 7 of 8 stacks active and about 16.8 TB/s per GPU. That reading is the outlet's inference; NVIDIA has not described the NVL8 configuration that way.

NVIDIA's two Rubin compute figures are not two speeds of the same job. Its NVL72 page marks the 50 PFLOPS NVFP4 inference figure as sparse, which counts the chip skipping half the weights in a fixed pattern, and the 35 PFLOPS NVFP4 training figure as dense.

The same split sits behind the HGX page's up to 10x throughput claim over HGX B200: NVIDIA's footnote sets sparse NVFP4 on Rubin against dense NVFP4 on the B200, and calls it projected. Compute was left untouched by the revision while memory bandwidth fell, and the spec sheets do not say how much of the sparse peak real decode work can use.

Limits of AMD's MI455X Paper Lead

The strongest counter is that NVIDIA lost little that buyers price. Compute is unchanged, scale-out bandwidth rose, and the NVL72 keeps its 20.7 TB of HBM4. ServeTheHome itself notes that not every workload is bound by memory or network bandwidth in the same way, and that the GPU compute ships at spec.

AMD's lead is also paper against paper. The 23.3 TB/s is AMD's peak figure, AMD's spec page still lists it, and no independent measurement of it exists either. AMD's own comparison table still sets MI455X against Vera Rubin at 22.0 TB/s, NVIDIA's old number, which shows how fast these tables age. CUDA's software lead does not appear on any spec sheet, and the buyers already lined up are not waiting on one. CoreWeave said on Oct. 21 that HGX Rubin NVL8 comes to its cloud this quarter, already quoting the 2 TB and 130 TB/s figures.

What It Means for Buyers and Rivals

At rack scale the paper gap is wide. StorageReview, reporting AMD's July 23 launch, put what AMD says is a 72-GPU Helios rack at 31 TB of HBM4, 1.7 PB/s of memory bandwidth, 260 TB/s of scale-up and 43 TB/s of scale-out, against NVIDIA's 20.7 TB, 1,400 TB/s, 216 TB/s and 32.4 TB/s for Vera Rubin NVL72. AMD's 3.6 TB/s per-GPU scale-up figure, which AMD labels bi-directional, matches the 3.6 TB/s NVIDIA first listed for NVLink; NVIDIA's page gives no direction label, so it is not a verified like-for-like. AMD says OpenAI, Meta, Anthropic, Microsoft and Oracle are adopting Helios, StorageReview reported.

For data-center operators, the change is in what each megawatt delivers rather than what it draws. NVIDIA's performance claims on both pages, such as up to 10x the token throughput of HGX B200 on the NVL8 (NVIDIA sets sparse NVFP4 on Rubin against dense NVFP4 on the B200), are footnoted as projected and subject to change, and NVIDIA has not said whether they were recalculated for the lower bandwidth. Buyers planning capacity in megawatts should ask for those projections on shipping specs before they sign. For AMD, the revision turns a capacity argument into a capacity-and-bandwidth argument it can make with NVIDIA's own numbers.

Earnings Dates to Watch for Rubin and MI455X

On Nov. 3 AMD reports third-quarter 2026 results, the first chance to hear whether MI455X and Helios ramp on schedule and still at 23.3 TB/s. On Nov. 10 CoreWeave reports, and its HGX Rubin NVL8 launch is due this quarter. On Nov. 17 NVIDIA reports third-quarter fiscal 2027 results, where analysts can ask the question its pages leave open: why the HBM4 and NVLink figures fell. The first independent bandwidth and token-rate measurements of either chip will settle more than any spec table.