Quantum Reality Check: IBM r3 Targets 10,000 Operations, r2 Passed 7,500

IBM says its Nighthawk r3 quantum processor is designed for 10,000 operations on 520 programmable qubits, yet the figure to watch is the 10,000, not the 520. Announced on Nov. 11, 2026, r3 has no availability date, so it is a target. The measured benchmark is IBM's Nighthawk r2, which produced accurate results on circuits of more than 7,500 gates on 120 qubits, according to IBM; a gate is a single operation. That accuracy comes from error mitigation, a statistical clean-up that needs many repeated runs, not from error correction.

What IBM, IQM and NVision Announced Since Oct. 21

Five results landed between Oct. 21 and Nov. 11, and they are different kinds of claim. On Nov. 11 IBM said r3 will be built to run 10,000 operations on 520 programmable qubits, with 2,034 "total physical qubits" in IBM's wording, and that it plans to link two of them into a 1,040-qubit system in 2027 (as Voltgrid reported). The 2,034 counts couplers and reset elements alongside the qubits a programmer addresses, according to SiliconANGLE.

On Nov. 5 IBM, AMD and Oak Ridge National Laboratory's Quantum Science Center launched a platform that places the 120-qubit Nighthawk next to ORNL's Umbra computing system, built on AMD Instinct MI355X GPUs, to study error correction (our report). On Oct. 29 IQM said its Emerald chip entangled all 54 qubits at a fidelity of 0.516, just above the 0.500 threshold for that claim (earlier coverage). An IBM preprint posted on Oct. 21 joined two 120-qubit chips with four 80 cm cables (our story). On Oct. 28 NVision published a Nature paper on a single carbene molecule that works as a qubit controlled with light, a spin-photon interface (the NVision story).

Measured vs. Targeted Quantum Figures, Sorted

The measured figures first. IBM reports that r2 gives accurate results, using error mitigation, on circuits of more than 7,500 gates and runs more than 100,000 circuits per second, 25 times the roughly 4,000 per second of its Heron fleet; both are IBM's own measurements. IBM's preprint, which is not peer reviewed, reports a mean state-transfer fidelity of 99.00% across four cable links, a best link of 99.29%, and a mean of 94.75% for two-qubit gates that span the two chips. IQM's 0.516 comes from the company's release, includes readout error mitigation at 54 qubits, and has no paper behind it. NVision's result is peer reviewed: the Nature paper reports one molecule under optical control, stable for more than an hour, with millisecond-scale coherence at 4.5 K.

Now the targets. IBM's r3 operation count, its 99.9% link-fidelity goal and the 1,040-qubit system are plans. So is NVision's end-of-2026 demonstration of molecules on a photonic chip, and so is its goal of 1,000 logical qubits, the error-protected kind explained below, by 2030. So are IBM's roadmap steps of 15,000 gates by 2028 and 100 million operations on 200 logical qubits by 2029.

Sources disagree on two points. IBM's release and its Nov. 11 blog post attach the 10,000 operations to the r3 chip. IBM's technology page attaches the figure to the system of two linked chips, and the caption on IBM's own release photo dates the capability to 2027. SiliconANGLE's report carries both versions. On link fidelity, IBM's release quotes 99.3%, which is the best of the four links rounded; the preprint and IBM's blog put the average at 99.00%. SiliconANGLE's 99.4% matches neither. We use the preprint.

Physical vs. Logical Qubits and Error Correction

A quantum program is a sequence of operations, called gates, applied to qubits. Each gate adds a little error. The qubit count sets how wide a program can be; the number of gates that can run before errors swamp the answer sets how much work fits inside that width.

The arithmetic shows why. Gate errors in late 2026 run between one in 100 and one in 1,000 operations, according to The Next Platform. IBM says gates on its Heron and Nighthawk chips do better, with errors measured in hundredths of a percent and as low as 0.04%, about one in 2,500. The 94.75% fidelity of the cross-chip gates means an error of 5.25% per gate. At that rate a program should expect one error for roughly every 19 gates that cross the cable (100 divided by 5.25, our calculation), against one in 2,500 inside a chip at best. Until the link closes that gap, cross-chip gates must stay rare, which limits what the second chip adds.

IBM's roadmap counts two-qubit gates in a whole circuit, and it set the steps in November 2025: 5,000 in 2025, up to 7,500 by the end of 2026, up to 10,000 in 2027 and up to 15,000 by 2028. Set against qubit counts, the gate count grows more slowly than the hardware. r2 has shown more than 7,500 gates on 120 qubits, at least 62.5 per qubit. The r3 target is 10,000 on 520 qubits, about 19 per qubit, or 9.6 if the 10,000 belongs to the 1,040-qubit linked system. These are our divisions and assume circuits that use every qubit, which IBM does not state. Qubits rise 4.3 times, operations at most 1.3 times.

A physical qubit is a real piece of hardware. A logical qubit is one qubit's worth of information spread across many physical ones so that errors can be caught and fixed. IBM compares it with classical majority voting: store a 0 as 000 and a 1 as 111, and a single flipped bit is outvoted.

The overhead is large. In Google's Nature paper on its Willow chip, one logical qubit used 101 physical qubits in a distance-7 surface code, one error-correcting scheme. Distance measures a code's strength: a higher distance cuts errors but needs more qubits. The logical error rate fell by a factor of 2.14 each time the code distance grew by 2, reaching 0.143% per error-correction cycle, and the logical memory outlived its best physical qubit by 2.4 times. That is a peer-reviewed measurement from December 2024, not necessarily the latest result. IBM's bivariate bicycle "gross code" packs 12 logical qubits into 288 physical qubits, which is 24 physical per logical for storing the information (our division; the 288 are 144 data and 144 check qubits, and the parts that compute on that memory add more). Google's 101 qubits are a distance-7 code, IBM's is distance 12. A distance-12 surface code would need 287 physical qubits per logical qubit (2 x 12 x 12 - 1; the same count gives 97 at distance 7, and Google's 101 adds four qubits for leakage removal), or 3,444 for 12 logical qubits, about 12 times IBM's 288, which fits IBM's claim of roughly 10 times fewer. That claim comes from the code IBM published in Nature in 2024 and built its June 2025 roadmap on, not from a running machine.

What a Useful Quantum Computer Needs

IBM says Starling in 2029 will run 100 million gates on 200 logical qubits at its Poughkeepsie, New York site. IBM, Oak Ridge and AMD describe the Department of Energy's Q Competition as targeting 100 logical qubits running 100,000 "hard operations," IBM's own unit, by late 2028. DOE's own announcement, dated Sept. 17, 2026, words it differently: at least 100 logical qubits capable of hundreds of millions of fault-tolerant operations, with extra prize pools for 150 and 200 logical qubits. IBM says its own demonstrations reached up to 70 logical qubits and 438 hard operations. On IBM's wording the gap is 100,000 divided by 438, about 228, which IBM rounds to a roughly 230-fold increase. Those 70 were error-detection experiments run with the University of Chicago: faulty runs were flagged and thrown away, which IBM says cut the effective gate error about tenfold. That is lighter protection than the error-corrected logical qubits above, so 70 here and one on Willow are not the same unit. IBM's wording for Starling shifted from 100 million quantum gates in June 2025 to 100 million hard operations on Nov. 11, 2026. IBM has not said whether that matches the unit behind the 438, so we compute no ratio.

For engineers and investors, the lesson is that the decoder, the classical computing step that reads the error checks and works out the corrections in real time, is a workload for conventional chips. IBM says its Relay-BP decoder is compact enough for an FPGA or ASIC and claims a 5x to 10x improvement over other leading decoders, without saying in that post which quantity improves. On Nov. 11 IBM said the decoder now meets Starling's requirements and that a dedicated decoder chip on 2-nanometer technology is in design. Google's decoder ran at 63 microseconds of latency at distance 5. The AMD GPUs at Oak Ridge are for research into error correction, decoding optimization and software orchestration, not IBM's production decoder. Cooling is part of the bill too: IBM said it joined two cryogenic modules in a single system that cooled below 15 millikelvin in under five days.

What to watch

IBM's roadmap lists Kookaburra, the first module to combine memory and logic for error correction, for 2026. IBM's Nov. 11 progress posts do not name it; they say the modular processors were redesigned to use fewer Josephson junctions, the superconducting switching elements such circuits are built from, about 2,000 per module instead of 5,000. As of Nov. 12, seven weeks of 2026 remain. Cockatoo, which should entangle modules, is listed for 2027, the same year IBM plans the 1,040-qubit r3 system. IBM wants link fidelity to rise from about 99% to 99.9%, with 10 chip-to-chip links, which it calls l-couplers, on r3 against four cables in the October preprint. NVision said its first prototype chips, made with a partner company, HyperLight, are due in the fourth quarter of 2026. IQM has not published a paper for the 54-qubit result, and its margin over the 0.500 threshold is 0.016. In late 2028, the target as IBM describes it will show whether 70 logical qubits and 438 hard operations can become 100 and 100,000.

Not confirmed yet: r3 has no ship date. Its operation count, the 99.9% link target, the 2027 system and Starling are plans, not measurements. The IBM linking paper is a preprint. IBM has not said whether the 10,000 operations belong to the r3 chip or to the two-chip system.